1. Field of the Invention
The present invention relates in general to column start signal generation circuits for memory devices, and more particularly to a column start signal generation circuit for a memory device which is capable of storing dummy data into a dummy cell, sensing an output level of a sense amplifier when the dummy data read from the dummy cell is amplified and outputted by the sense amplifier and generating a column start signal at the moment that the sensed level becomes a desired level, so as to enhance an operating speed of the memory device.
2. Description of the Prior Art
Generally, in reading data stored in a memory cell of a memory device, a column start signal is used as one of drive signals to a column switch (Y switch) which transfers the data read from the memory cell to an output buffer.
Referring to FIG. 1, there is shown a schematic block diagram of a conventional column start signal generation circuit for a memory device. As shown in this drawing, the conventional column start signal generation circuit comprises a delay part 1 for delaying a sense amplification enable signal SAE inputted therein and outputting the delayed sense amplification enable signal as a column start signal CS.
When the data is read from the memory cell of the memory device, the column switch generally has an indistinct drive point because it is unknown whether the data read from the memory cell is completely sensed by a sense amplifier.
For this reason, in the conventional column start signal generation circuit, the delay part 1 delays the sense amplification enable signal SAE by an anticipated time margin which is taken for the sense amplifier to completely sense the data read from the memory cell, so as to generate the column start signal CS.
However, in the above-mentioned conventional column start signal generation circuit, when the anticipated time margin is smaller than an actual margin, the sense amplifier is not operated sufficiently, resulting in generation of a small voltage difference between a true bit line and a complementary bit line connected to the sense amplifier. Such a small voltage difference between the true bit line and the complementary bit line results in a faulty operation of the sense amplifier such as an output inversion.
On the other hand, in the case where the anticipated time margin is larger than the actual margin, the column start signal CS is too late generated from the delay part 1 and the column switch is driven late to that extent. This results in a degradation in an operating speed of the memory device.